Screen and stencil printing technology has been used for a number of years for printed circuit board (PCB) manufacturing and surface mount component assembly of PCBs. The green-colored solder mask, numbering and white component outlines found on many inexpensive PCBs is an epoxy material applied using a screen printing process. Prior to placing surface-mount components on a circuit board, solder paste is normally applied over the copper pads using a stencil printing method.
These processes are similar to ancient silk-screening methods used for imaging patterns directly onto paper and textile products. Modern screens comprise of an interwoven mesh of thin stainless steel wire that supports a photo-imaged emulsion layer. Openings within the emulsion layer enable a variety of inks and epoxy pastes to be squeezed through and transferred onto a flat surface to reproduce the pattern imaged within the emulsion layer. Stencil printing is fairly similar in concept, except that the wire mesh is substituted with a thin metal or polymer foil through which a pattern of apertures have been cut, etched or plated.
Wafer fabrication has long been ruled by concern for particulate control so as to attain the minimum feature sizes essential for state-of-art integrated circuits (ICs). The comparatively course geometry boundaries for both screen and stencil printing technology has, consequently, been demoted to “back-end” packaging of integrated circuits, or PCB level connections. However, the earlier clear distinction between front and back-end wafer processing is becoming distorted because of the need to perform more “packaging” functions while the chips are in wafer-form. 
With today’s growing need to decrease component size and processing costs, screen and stencil-print technology is finding new application together with “front-end” wafer fabrication. An example of this is stencil-printed solder paste on entire wafers for flip chip interconnections. And in recent times, wafer-level screen-printed coatings are being developed for the protection of bare die.
Non-vacuum based wafer coatings are usually applied by a spin-on method using the same equipment intended for photo resist patterning. These coatings are usually solvent-based and form very thin layers. Screen-printed inks and epoxies, on the other hand, are patterned straight away onto the wafer’s surface and do not need subsequent steps to mask, expose and develop a patterned layer. Since these materials are formulated for screen/stencil print processing, they are usually solvent-free and possess higher solids content than spin-on materials. Hence, these coatings are inclined to be thicker and more scratch-resistant to provide improved protection of minimally packaged ICs. Some benefits of both screen-printed and spin-on coating methods are summarized below.
Screen-printing silver epoxies for surface mount applications is properly documented. [2,3,4] At the PCB level, the incentives were high volume area array assembly, because of better throughput over dispensing techniques, while being a drop in replacement for solder paste. Manufacturing with silver epoxy paste, would need to be as simple, established and wide-scale as stencil printing solder paste. One group suggested a model for stencil printing process, followed by a factorial design of experiments (DOE) for improvement of the final print patterning. 
Due to the momentum expressed above, at the PCB or 2nd level interconnect, Epoxy Technology decided to examine the feasibility of patterning by screen-printing at the chip, or 1st level interconnect. Although screen-printing cannot start to match the fine geometries realizable using conventional photoimagable polymers, Epoxy Technology feels it is typically sufficient for Chip Scale Packaging (CSP), Flip Chip and other wafer-level coating requirements. A few examples include protective coating over bio-MEMs devices, passivation isolation of redistributed bond pads, alpha particle protection of memory die, and perimeter edge sealing of glass windows or lids over opto-ICs.
The screen printer used for these experimental projects is an MPM-SPM with a custom vacuum platen for holding wafers up to 300 mm diameter. A Leitz Secolux 6x6 Microscope and Heidenhain digital counter were used to measure the thickness of the coatings using a variance in focal-height from the substrate to the top-surface of the coatings. Thickness measurements using this technique are not as accurate as would be acquired from viewing cross-sections, but are acceptable for the purposes of these assessments. Usually the epoxy coating thickness would be measured both before and after curing to assess the amount of shrinkage that may happen.
The wafers were cured in a Lindberg Blue M (model MO1450A) convection-type oven, pre-heated to the appropriate curing temperature. The epoxy materials were not stirred by hand or degassed prior to printing so as to maintain the correct viscosity and prevent air from becoming added into the material. The epoxy material would normally be premixed on a three-roll mill or high-shear, counter-rotating, centrifugal mixer, based on the material being formulated. The centrifugal mixer works with sufficient speed and shear forces so that a substantial amount of air is removed from the mixed epoxy.
Figure 1 is a photo of a portion of a fingerprint sensor with two varied screen-printed materials: (a) a clear, UV-cured, orange-peel textured, polymer coating to protect the sensor’s cells from scratch and impact damage, and (b) a white border of B-staged epoxy to stick the sensor chip to a flexible circuit within a cut-out window. Selecting an optimum thickness, one enough to ensure protection of the sensor surface without sacrificing the chip’s imaging sensitivity, was derived by printing and curing multiple layers of UV-cured epoxy on individual bare die.
One to four layers were printed and cured, measuring in thickness from 9 µm to 38 µm. Once the suitable thickness was chosen (30-32 µm), a screen mesh (400 mesh, 0.00075” wire diameter) and emulsion thickness (0.0017”) were chosen to coat a whole 200 mm wafer using a single print. A similar method was used to create an ideal thickness and B-stage cure schedule for the white adhesive border surrounding each sensor chip.
Figure 1. MEMs finger print sensor containing UV cured epoxy coating in the center, with B-stage epoxy resin along the 4 edges.
Another fingerprint chip application required a thin “metallic” colored coating over the surface. A custom formulation, comprising of aluminum flake mixed into a solvent-based resin, realized the desired color and texture for this specific chip. To evaluate the printing resolution, the customer created and submitted a test pattern with graduated and tapered openings. Figure 2 illustrates a close-up section of test prints composed of a single, double and triple layer. Before and after wafer printing, each wafer was weighed to measure how much epoxy was needed for each layer. The average weight for a 25 µm thick layer, spread across a 150 mm wafer, was 0.25 g. After curing for 30 minutes at 200 °C, each layer shrank to an average thickness of 12-15 µm.
Each wafer coating was exposed to mechanical stress testing. Drop tests of 20 cm and scratch resistance were done.
For drop tests, a 1 mm diameter medium point, carbide tip, BIC pen, weighing 6 g, was used. A zero-degree angle, respective to the normal, was used for a no-tilt incidence. The number of units comprised of nine standard spin-on coated wafers, three un-coated, and two each EPO-TEK coated wafers. The same pen was used for the scratch-testing, comprising of 1-2 lb load, with manual force exerted across 80% of the sensor region. A similar pen was used for the diamond-tip micro-scratch tester, using 0.2 lb load, at a controlled velocity of 10 mm/minute, across a distance of 3 mm.
Figure 2. Test Pattern of MEMs finger print sensor having 400 micron mask off area, with tapered and graduated lines for assessing the fine-print resolution.
The results of the drop test are illustrated in Figure 3. Two thicknesses of EPO-TEK screen printable coating were compared against the spin-on polyimide control and un-coated biometric sensors. The results indicate, as predicted, that a 12 µm layer of EPO-TEK coating provided better protection than 5 µm, and better than a 6 µm layer of spin-on polyimide. Table 1 offers a final summary of the scratch resistance testing, carbide tip versus diamond. Observations that the 12 µm screen print coating protected the die better than 5 µm coating, as well as the spin-on coating, suit properly with the drop tests shown in figure 3.
Memory wafers are key candidates for chip scale packaging, because of the need of higher integration at a fraction of the PCB real estate. To protect the chip’s surface from handling damage and alpha particle induced bit errors, an epoxy-polyimide-based coating was developed for screen-print patterning. A boron-nitride filler was added as a non-abrasive filler or thixoptropic agent, enabling good pitch geometry and patterning, as well as to help enhance thermal transfer from the die’s surface to PCB.
Figure 4 illustrates the pattern for a redistributed ball grid array with 0.009” diameter openings for solder ball placement. The print thickness measured 20-22 µm before curing and 14-15 µm after curing, which was very near the 12 µm target. Each wafer had 250 chips, with 128 I/Os per chip. The SRAM die had dimensions of 367 mil x 317 mil.
Only 0.5 g of epoxy was required to cover a 200 mm wafer using a 400 mesh screen with 0.0002” emulsion. That means around 900 wafers can be screen print coated from 1 lb of polymer passivation. In the competing technology, Epoxy Technology has deduced the materials and labor cost linked with spin-on processes using photo-lithography to be around $35 per wafer, a process that produces more waste than what is used. Epoxy Technology process is fully recyclable, producing no waste, thus the technology is highly compelling, considering the costs benefits.
A second study involving memory die, in this case DRAM, was investigated. In contrast to the application above, which had area array bond pads or redistributed bond pads, this SRAM device used traditional perimeter layout around two edges only. A sketch of the chip layout is illustrated in Figure 5. The die size was 248 mil x 146 mil and had 54 I/Os per chip. The chips were arranged in a field of 6x3, with 59 fields per 8” wafer, or approximately 1062 chips per wafer.
Epoxy Technology selected an effective screen print coverage of 227 mil x 146 mil. One half of the 21 mil net difference is the quantity of “pull back” of polymer coating per edge. The 10 mil opening was targeted because the bond pad I/Os were 4 mil square, plus an extra 3 mils was incorporated to each side of the pads. Here, there is no need to print polymer coating up to the edges of each I/O, jeopardizing an overcoat of organic residue on the wire bond pads (see Figure 6B).
Table 2 reveals the results of the wire bond quality tests. Although wire pull was found to be satisfactory, ball shear was 4 g below spec. The trend of NSOP, or “nonstick on pads” may have been noticed. The spec of 18 g was not attained.
Epoxy Technology theorizes that two things can be enhanced. First, a purge of air or N2 gas during box oven curing may lessen some of the outgassed hydrocarbons from redepositing onto the surface of the I/Os. Secondly, a “pull-back” of 3 mils might not have been sufficient to prevent polymer passivation from over coating the strips of wire bond pads. Figures 6A and 6B illustrate an acceptable die that has been wire bonded versus a close-up of one die that had been inadequately over-coated, producing NSOP.
Figure 6A. Wire bonded memory die showing two mask-off areas on the ends. Figure 6B. Possible source of low wirebond shear strength due to organic bleed-out onto the I/Os.
Adhesive sealing around the four edges of glass cover slips, is a common packaging technique for CSP devices. A glass-Si-glass packaging structure allows for transmission of visible light range 350–900 nm, enabling opto-electronic devices to be attained, such as CCD and CMOS image sensors, found in digital cameras and cell phones, as well as machine vision applications such as copiers, scanners and optical pick-up units for DVDs. While some methods of adhesive sealing might use dispensers and capillary forces of medium viscosity resins , Epoxy Technology finds edge sealing to be possible by screen-print approaches at the wafer level, instead of single chip glass level.
Figure 7. 5 mm x 5 mm glass die with 4-edge perimeter seal using B-stage epoxy. The chips were arrayed across the wafer in a 25 x 25 format.
Epoxy Technology used 8 mil borosilcate glass wafers, which were 14 cm x 14 cm square, although they could have been received in traditional 8” wafer format. Figure 7 illustrates the 1 up chip layout. 200 µm line widths were printed along the four edges of the chip. Each chip measured 5 mm x 5 mm. A 200 µm step-and-repeat was used for the X and Y axis saw streets. A total of 625 chips were arranged in a 25 x 25 format.
Final dried print thickness was determined to be 25 µm for a single print, 40 µm for double print and 60 µm for a triple print. A 325 mesh screen using 1.1 mil wire diameter and 0.4 mil emulsion was employed for the project. A solvent comprising B-stageable epoxy was selected as the adhesive / sealant. This epoxy lends itself to high volume assembly in a down-stream process. Final (A-stage) curing to the second surface can be achieved using 160 °C / 15 seconds + 15N of pressure.
Concerning applications, it is typical in the MEMs industry, for glass lids to act as package barrier, or a protective layer above the active chip.  Examples are micro-mirror arrays, mainly driven by Texas Instruments and found in fiber optic switching products, and “cap wafers” found in pressure sensors or accelerometers. Figure 8 is a schematic diagram of both devices. With the micro-mirror array, edge sealing of the glass window must be attained, so that IR light from the optical beam pathway is not limited.
In fiber optic switching, laser beams of IR light are re-directed by the on-off pulses of the rotating mirrors. Cap wafers may also be referred to as “structured”, or “support wafers”, as they “support” the active MEMs chip by acting like a firm host carrier, as well as sealing out moisture, atmosphere and other contaminants that could destroy the IC.
Figure 9 illustrates the test pattern that was used, and the cured photo. The smallest row reveals a masked off region of 5 mil x 5 mil pads, spaced at 8 mil, with the largest row having 12 mil x 12 mil pads at 18 mil pitch. The array was intended to be an hour-glass shape, so that Epoxy Technology could monitor if the direction of the squeegee stroke impacted the shape of the masked-off pads. Most wire bonds pads are 4 mil x 4 mil, hence the decision to investigate whether or not I/Os could be masked off.
Epoxy Technology used a calendard 325 mesh having 0.75 mil diameter stainless steel wire, with 0.5 mil emulsion. They advise an amber-colored, polymer squeegee blade, which rolls easily across the metal mesh. Print parameters need to be enhanced for any screen print job, based on print thickness, pitch, or shape of the masked off region, but they discovered the following parameters to work well: stroke velocity of 1-1.5” per second; snap-off distance of 60-80 mils, stroke force of 20 -30 lbs, squeegee angle 45 degree.
Screen printable polymers acting like passivation, are certain to play a role in wafer level packaging. Epoxy Technology has demonstrated that it can be used in several applications such as memory device, protection of bio-MEMs finger print sensors and opto-electronic packaging. A test pattern was built, so as to monitor the smallest pattern or array that could be masked-off.
Epoxy Technology also believes it is beneficial as a buffer coating layer, in its cured form, on the top side of wafers, because of recent packaging trends like 3D or chip stacking. The, “industry is working on new ultra-integration strategies, such as SiP or 3D chip staking, the latter achieved by wafer-to-wafer bonding, or die-to-wafer”, says Peter Singer, Editor-in-chief of Semiconductor International.  Epoxy Technology product is the perfect candidate for adhesive applications at the wafer level.
In order for 3D chip stacking to happen, wafer thinning technologies must be realized. Back-lapping, or wafer thinning, involves positioning the wafer face down into wax and grinding the silicon off the back side until the preferred thickness is attained. This mechanical stress can tear off metallization lines, cause electrical shorts, or “dead” devices. It has been recorded that when using top-side polyimide passivation coatings, wafer yields grew from 53.7% to 88% compared with uncoated devices, after probe card testing.  With ultra-integration, it is typical for 2-, 3-, 4- or more stacked die in package, occupying the same dimensions as single-chip package in the past.  Virtually 85% of DRAM memory devices are conveyed as modules, with 3D stacking playing a crucial role. 
In opto-devices, work at Georgia Tech is ongoing for chips that communicate with each other by optical and electrical signals.  Definitely glass lids, or windows, will be used for protecting, sealing and conveying the light properly, and wafer level screen printing of adhesives and coatings will be necessary.
2. Estes, R. H., Pernice, R. F., and Hannafin, J. J., “Evaluation of Isotropically Conductive Adhesives for Solder Replacements”. Proceedings of the ISHM Conference, Boston, MA., 1994, pp. 561-565.
3. Li, L., Morris, J.E., “Reliability and Failure Mechanisms of Isotropically Conductive Adhesive Joints”, Proceedings of the IEEE Conference, 1995, pp. 114-120.
4. Breed, Steven., “Stencil Adhesive Deposition”, Surface Mount Technology Magazine, January, 1998, pp. 68-73.
5. Lin, J. K., Lytle, W., Scharr, T., Subrahmanyan, Sharma, R., “Conductive Polymer Bump Interconnects”, Proceedings of the ECTC Conference, Orlando, FL, 1996, pp. 1059-1968.
7. Cupers, D., Van Doorelaer, G., Van Den Steen, J., “Assembly of an XGA 0.9” LcoS Display using Inorganic Alignment Layers for VAN LC”, Proceedings of the European Society Informat Display Conference, Paris, 2003, pp. unknown
8. Gilleo, K., “MEMs Packaging Issues and Materials”, Journal of Advancing Microelectronics, 2000, Vol.27, 6, pp. 9-13.
10. Kulesza, F. W., Estes, R.H., Spanjer, K., “A Screen Printable Polyimide Coating for Silicon Wafers”, Solid State Technology Magazine, Jan., 1988, pp. unknown
11. Levine, Bernard, “Packaging Foundries at the Cutting Edge”, Semiconductor Manufacturing Magazine, Sep., 2004, p. 37.
This information has been sourced, reviewed and adapted from materials provided by Epoxy Technology, Inc.
Epoxy Technology, Inc.. (2019, July 17). Wafer Level Packaging with Screen Printable Polymers. AZoM. Retrieved on January 26, 2020 from https://www.azom.com/article.aspx?ArticleID=14669.
Epoxy Technology, Inc.. "Wafer Level Packaging with Screen Printable Polymers". AZoM. 26 January 2020. .
Epoxy Technology, Inc.. "Wafer Level Packaging with Screen Printable Polymers". AZoM. https://www.azom.com/article.aspx?ArticleID=14669. (accessed January 26, 2020).
Epoxy Technology, Inc.. 2019. Wafer Level Packaging with Screen Printable Polymers. AZoM, viewed 26 January 2020, https://www.azom.com/article.aspx?ArticleID=14669.
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